ARCHITECTURE(ADSP-BF533)

SEARCH_DIR( $ADI_DSP\Blackfin\lib )

$OBJECTS = $COMMAND_LINE_OBJECTS;
//$LIBRARIES = librt.dlb;

MEMORY
{
    
//	DATA_A		{ TYPE(RAM) START(0xf00000a0) END(0xf0000200) WIDTH(8) }
//	DATA_B		{ TYPE(RAM) START(0x00100000) END(0x001FFFFF) WIDTH(8) }
//	PROGRAM		{ TYPE(RAM) START(0x00200000) END(0x002FFFFF) WIDTH(8) }
//	STACK		{ TYPE(RAM) START(0x00300000) END(0x003FFFFF) WIDTH(8) }
//	SYS_MMR		{ TYPE(RAM) START(0xFFC00000) END(0xFFDFFFFF) WIDTH(8) }
//	CORE_MMR	{ TYPE(RAM) START(0xFFE00000) END(0xFFFFFFFF) WIDTH(8) }
//	PROGRAM		{ TYPE(RAM) START(0xEF000000) END(0xEF0003FF) WIDTH(8) } //Boot Rom
	PROGRAM		{ TYPE(RAM) START(0xFFA00000) END(0xFFA07fff) WIDTH(8) } //L2
	SDRAM		{ TYPE(RAM) START(0x00000000) END(0x07FFFFFF) WIDTH(8) } //SDRAM
//	PROGRAM		{ TYPE(RAM) START(0x20000000) END(0x23FFFFFF) WIDTH(8) } //ASYNC BANK 0
//	L1_CODE		{ TYPE(RAM) START(0xFFA00000) END(0xFFA03FFF) WIDTH(8) } //L1 Code
//	L1_DATA		{ TYPE(RAM) START(0xFF800000) END(0xFF803FFF) WIDTH(8) } //L1 Data
//	HEADER		{ TYPE(RAM) START(0xF003FFE0) END(0xF003FFE6) WIDTH(16)}
//	BLOCK		{ TYPE(RAM) START(0xF003FFEA) END(0xF003FFF2) WIDTH(16)}
//	DUMMY		{ TYPE(RAM) START(0xF003FFF4) END(0XF003FFFE) WIDTH(16)}
}


PROCESSOR p0
{
    OUTPUT( $COMMAND_LINE_OUTPUT_FILE )

    SECTIONS
    {
        code
        {
        	// Align all code sections on 2 byte boundary
        	INPUT_SECTION_ALIGN(2)
        	INPUT_SECTIONS( $OBJECTS(program))
		}>PROGRAM
		
	SDRAM
	{
		INPUT_SECTION_ALIGN(1)
		INPUT_SECTIONS( $OBJECTS(sdram) )
	} >SDRAM	
	
	stack
    {
    	// The data sections shouldn't be aligned.
    	INPUT_SECTION_ALIGN(1) 
    	INPUT_SECTIONS( $OBJECTS(stack))
//		}>STACK    
	}>PROGRAM
    }
}

